FIG. 1 shows a SONOS (semiconductor oxide nitride oxide semiconductor) flash memory cell 100. The SONOS flash memory cell 100 includes a drain bit-line junction 102 and a source bit-line junction 104 formed within a semiconductor substrate 106. In addition, an ONO (oxide nitride oxide) stack comprised of a bottom oxide 108, a nitride 110, and a top oxide 112 is formed on the semiconductor substrate 106. Furthermore, a control gate 114 comprised of polysilicon is formed on the ONO stack.
A variable amount of charge carriers such as electrons is stored in the nitride 110 for storing bit information in the SONOS flash memory cell 100, as known to one of ordinary skill in the art. FIG. 2 shows a lay-out of an array 120 of such SONOS flash memory cells including an ONO stack 122 formed over a core active area 124. First, second, third, and fourth source/drain bit-line junctions 132, 134, 136, and 138, respectively, are formed within the core active area 124.
In addition, first, second, third, and fourth word-line gates 142, 144, 146, and 148, respectively, are formed across the source/drain bit-line junctions 132, 134, 136, and 138. Furthermore, bit-line junction contacts 143 are formed on the source/drain bit-line junctions 132, 134, 136, and 138, and word-line contacts 145 are formed on the word-line gates 142, 144, 146, and 148.
Each SONOS flash memory cell in the array 120 is formed by a portion 147 of a word-line gate over two adjacent source/drain bit-line junctions. Thus, a row of SONOS flash memory cells in the array 120 share a common word-line gate as the control gates of such SONOS flash memory cells. In addition, a column of SONOS flash memory cells share same source/drain bit-line junctions.
FIG. 3 shows a cross-sectional view across dashed line 152 of FIG. 2 along the source/drain bit-line junction 138 formed in the semiconductor substrate 106. Referring to FIG. 3, a bottom oxide layer 154, a nitride layer 156, and a top oxide layer 158 of the ONO stack 122 are formed on the source/drain bit-line junction 138. The word-line gates 144, 146, and 148 are formed across the source/drain bit-line junction 138. In addition, a metal silicide 160 is formed on the word-line gates 144, 146, and 148 for providing low resistance contact to the word-line gates 144, 146, and 148. The bit-line junction contact 143 is formed through the ONO stack 122 to contact the source/drain bit-line junction 138.
Additionally referring to FIG. 3, spacers 162 are formed to the sides of the word-line gates 144, 146, and 148. When the spacers 162 are comprised of silicon nitride (SiXNY), a liner layer 164 is formed between the spacers 162 and the word-line gates 144, 146, and 148, the metal silicides 160, and the top oxide layer 158. Such a liner layer 164 is comprised of silicon dioxide (SiO2) in the prior art for a more stable interface between such structures 162, 160, 158, 144, 146, and 148.
Unfortunately, the oxide liner layer 164 does not significantly prevent hydrogen from reaching the nitride layer 156. Such hydrogen reaching the nitride layer 156 causes charge leakage from the nitride layer 156 which in turn degrades the performance of the SONOS flash memory cells.
In addition, the oxide liner layer 164 may not be used as an etch stop layer for preventing over-etch in a periphery region of the flash memory device. FIG. 4 shows a flash memory device 170 including a core region 172 and a periphery region 174. The core region 172 has the array 120 of SONOS flash memory cells fabricated therein, and the periphery region 174 has a logic circuit fabricated therein for controlling operation of the SONOS flash memory cells in the core region 172.
Referring to FIG. 5, a periphery active area 176 within the periphery region 174 is surrounded by a STI (shallow trench isolation) structure 178. A junction 175 for a device such as a MOSFET (metal oxide semiconductor field effect transistor) is fabricated for the logic circuit in the periphery region 174. An interlayer insulating material 180, typically comprised of silicon dioxide (SiO2) doped with boron or phosphorous or both, is deposited on the semiconductor substrate 106.
An opening 182 is formed through the interlayer insulating material 180, and a contact plug 184 is formed to fill the opening 182 for making contact to the junction 175. A metal interconnect 186 is formed on the contact plug 184. Because the STI structure 178 and the interlayer insulating material 180 are both comprised of silicon dioxide (SiO2), misalignment of the opening 182 with respect to the junction 175 and an over-etch of the interlayer insulating material 180 results in an etched portion 188 of the STI structure 178.
Undesired leakage current results when the contact plug 184 fills the etched portion 188 of the STI structure 178. Referring to FIGS. 3 and 5, when the liner layer 164 is also comprised of silicon dioxide (SiO2), such a liner layer 164 cannot be used as an etch stop for preventing such a formation of the etched portion 188 of the STI structure 178.
Furthermore, when the liner layer 164 is comprised of silicon dioxide (SiO2), the metal silicide 160 formed on the word-line gates may be disadvantageously formed on and between the source/drain bit-line junctions. FIG. 6 shows a cross-sectional view along line 190 of FIG. 2, and elements having the same reference numbers in FIGS. 3 and 6 refer to elements having similar structure and function.
However, FIG. 6 is the cross-sectional view during etching of the silicon nitride (SiXNY) for forming the spacers 162. If such nitride is over-etched, then exposed portions (between the word-line gates 146 and 148) of the top oxide liner layer 158 and the nitride layer 156 of the ONO stack are etched away as illustrated in FIG. 6.
Referring to FIG. 7, the exposed portion of the bottom oxide liner layer 154 is etched away during a subsequent cleaning process. Referring to FIG. 8, a metal silicide 160 such as cobalt silicide is formed with the polysilicon of the word-line gates 142, 144, 146, and 148. However, the metal silicide 160 is also formed with any exposed portions of the semiconductor substrate 106 including between the word-line gates 146 and 148.
Such a metal silicide 160 formed on the semiconductor substrate 106 disadvantageously leads to bit-line to bit-line leakage current. Bit-line to bit-line leakage current refers to undesired current between the source/drain bit-line junctions 132, 134, 136, and 138, such as the path shown with a dashed line 198 in FIG. 2.